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Commercial/ Industrial
PA7024
PA7024 PEELTM Array
Programmable Electrically Erasable Logic Array Features
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CMOS Electrically Erasable Technology - Reprogrammable in 24-pin DIP, SOIC and 28-pin PLCC packages -Optional JN package for 22V10 power/ground compatibility Most Powerful 24-pin PLD Available - 20 I/Os, 2 inputs/clocks, 40 registers/latches - 40 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried Flexible Logic Cell - Multiple output functions per cell - D,T and JK registers with special features - Independent or global clocks, resets, presets, clock polarity and output enables -Sum of products logic for output enable
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High-Speed Commercial and Industrial Versions - As fast as 10ns/15ns (tpdi/tpdx), 71.4MHz (fMAX) - Industrial grade available for 4.5 to 5.5V Vcc and -40 to +85C temperatures Ideal for Combinatorial, Synchronous and Asynchronous Logic Applications - Integration of multiple PLDs and random logic - Buried counters, complex state-machines - Comparators, decoders, multiplexers and other wide-gate functions Development and Programmer Support - ICT PLACE Development Software - Fitters for ABEL, CUPL and other software -Programming support by ICT PDS-3 and popular thirdparty programmers
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General Description
The PA7024 is a member of the Programmable Electrically Erasable Logic (PEELTM) Array family based on ICT's CMOS EEPROM technology. PEELTM Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today's programmable logic designs. The PA7024 is by far the most powerful 24-pin PLD available today with 20 I/O pins, 2 input/global-clocks and 40 registers/latches (20 buried logic cells and 20 I/O registers/latches). Its logic array implements 84 sum-of-product logic functions that share 80 product terms. The PA7024's logic and I/O cells (LCCs, IOCs) are extremely flexible, offering two output functions per logic cell (a total of 40 for all 20 logic cells). Logic cells are configurable as D, T, and JK registers with independent or global clocks, resets, presets, clock polarity, and other special features. This makes them suitable for a wide variety of combinatorial, synchronous and asynchronous logic applications. With pin compatibility and super-set functionality to most 24-pin PLDs, (22V10, EP610/630, GAL6002), the PA7024 can implement designs that exceed the architectures of such devices. The PA7024 supports speeds as fast as 10ns/15ns (tpdi/tpdx) and 71.4MHz (fMAX) at moderate power consumption 120mA (85mA typical). Packaging includes 24-pin DIP SOIC and 28-pin PLCC (see Figure , 1). Development and programming support for the PA7024 is provided by ICT and popular third-party development tool manufacturers.
Figure 1: Pin Configuration
Figure 2. Block Diagram
DIP
SOIC
PLCC-J
PLCC-JN
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PA7024
Table 1. Absolute Maximum Ratings Symbol
VCC VI, VO IO TST TLT
This device has been designed and tested for the recommended operating conditions. Proper operation outside these levels is not guaranteed. Exposure to absolute maximum ratings may cause permanent damage.
Parameter
Supply Voltage Voltage Applied to Any Pin2 Output Current Storage Temperature Lead Temperature
Conditions
Relative to Ground Relative to Ground1 Per pin (IOL, IOH)
Ratings
-0.5 to + 7.0 -0.5 to VCC + 0.6 25 -65 to + 150
Unit
V V mA C C
Soldering 10 seconds
+300
Table 2. Operating Ranges Symbol
VCC
Parameter
Supply Voltage
Conditions
Commercial Industrial Commercial Industrial See Note 2 See Note 2 See Note 2
Min
4.75 4.5 0 -40
Max
5.25 5.5 +70 +85 20 20 250
Unit
V
TA TR TF TRVCC
Ambient Temperature Clock Rise Time Clock Fall Time VCC Rise Time
C ns ns ms
Table 3. D.C. Electrical Characteristics over the recommended operating conditions Symbol
VOH VOHC VOL VOLC VIH VIL IIL IOZ ISC
Parameter
Output HIGH Voltage - TTL Output HIGH Voltage - CMOS Output LOW Voltage - TTL Output LOW Voltage - CMOS Input HIGH Level Input LOW Level Input Leakage Current Output Leakage Current Output Short Circuit Current4
Conditions
VCC = Min, IOH = -4.0mA VCC = Min, IOH = -10A VCC = Min, IOL = 16mA VCC = Min, IOL = 10A
Min
2.4 VCC - 0.3
Max
Unit
V V
0.5 0.15 2.0 -0.3 VCC + 0.3 0.8 10 10 -30 -15 -120 120 85 (typ.) 17 120 120 130 6 12
V V V V A A mA
VCC = Max, GND VIN VCC I/O = High-Z, GND VO VCC VCC = 5V, VO = 0.5V, TA= 25C VIN = 0V or VCC3,11 f = 25MHz All outputs disabled4
ICC11
VCC Current
-20 -25 I-25
mA
CIN7 COUT7
Input Capacitance5 Output Capacitance5
TA = 25C, VCC = 5.0V @ f = 1 MHz
pF pF
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PA7024
Table 1. A.C Electrical Characteristics Combinatorial -15 Symbol
tPDI tPDX tIA tAL tLC tLO tOD, tOE tOX
Over the operating range
Parameter6,12
Propagation delay Internal (tAL + tLC) Propagation delay External (tIA + tAL +tLC + tLO) Input or I/O pin to array input Array input to LCC LCC input to LCC output10 LCC output to output pin Output Disable, Enable from LCC output7
Min
Max
10 15 2 9 1 3 3 15
-20 Min Max
13 20 2 12 1 5 5 20
I -25 Min Max
17 25 2 16 1 6 6 25
Unit
ns ns ns ns ns ns ns ns
Output Disable, Enable from input pin7
Combinatorial Timing - Waveforms and Block Diagram
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PA7024
Table 1. A.C. Electrical Characteristics Sequential over the operating range
-15
Symbol
tSCI tSCX tCOI tCOX tHX tSK tAK tHK tSI tHI tPK tSPI tHPI tCK tCW fMAX1 fMAX2 fMAX3 fMAX4 fTGL tPR tST tAW tRT tRTV tRTC tRW tRESET
-20 Min
9 11 8 12 8 13 0 3 1 4 0 4 6 7 0 6 7 7 7 71.4 62.5 55.5 50.0 71.4 1 12 58.8 52.6 45.5 41.6 71.4 1 15 8 6 1 7 8 1 9 10 5 5 10 8 8 0 7 0 4 1 4 0 4/3
I-25 Min
15 17 8 13
Parameter
6,12
Min
6 8
Max
Max
Max
Unit
ns ns ns ns ns ns ns ns ns ns
Internal set-up to system clock8 - LCC14 (tAL + tSK + tLC - tCK) Input16 (EXT.) set-up to system clock, - LCC (tIA + tSCI) System-clock to Array Int. - LCC/IOC/INC14 (tCK +tLC) System-clock to Output Ext. - LCC (tCOI + tLO) Input hold time from system clock - LCC LCC Input set-up to async. clock13 - LCC Clock at LCC or IOC - LCC output LCC input hold time from system clock - LCC Input set-up to system clock - IOC/INC14 (tSK - tCK) Input hold time from system clock - IOC/INC14 (tSK - tCK) Array input to IOC PCLK clock Input set-up to PCLK clock
18
0 3 1 4 0 4
9
ns ns ns
- IOC/INC (tSK-tPK-tIA)
16 16
0 5
Input hold from PCLK clock
18
- IOC/INC (tPK+tIA-tSK)
System-clock delay to LCC/IOCINC System-clock low or high pulse width Max. system-clock frequency Int/Int 1/(tSCI + tCOI) Max. system-clock frequency Ext/Int 1/(tSCX + tCOI) Max. system-clock frequency Int/Ext 1/(tSCI + tCOX) Max. system-clock frequency Ext/Ext 1/(tSCX + tCOX) Max. system-clock toggle frequency 1/(tCW + tCW)9 LCC presents/reset to LCC output Input to Global Cell present/reset (tIA + tAL + tPR) Asynch. preset/reset pulse width Input to LCC Reg-Type (RT) LCC Reg-Type to LCC output register change Input to Global Cell register-type change (tRT + tRTV) Asynch. Reg-Type pulse width Power-on reset time for registers in clear state
2
7
ns ns
7
43.5 40.0 35.7 33.3 62.5 2 20
MHz MHz MHz MHz MHz ns ns ns
8
10 2 12
ns ns ns ns
10
5
s
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PA7024
Sequential Timing - Waveforms and Block Diagram
Notes
1. Minimum DC input is -0.5V, however inputs may undershoot to -2.0V for periods less than 20ns. 2. Test points for Clock and VCC in tR,tF,tCL,tCH, and tRESET are referenced at 10% and 90% levels. 3. I/O pins are 0V or VCC. 4. Test one output at a time for a duration of less than 1 sec. 5. Capacitances are tested on a sample basis. 6. Test conditions assume: signal transition times of 5ns or less from the 10% and 90% points, timing reference levels of 1.5V (unless otherwise specified). 7. tOE is measured from input transition to VREF 0.1V (See test loads for VREF value). tOD is measured from input transition to VOH -0.1Vor VOL +0.1V. 8. "System-clock" refers to pin 1 or 13 (2 or 16 PLCC) high speed clocks. 9. For T or JK registers in toggle (divide by 2) operation only. 10. For combinatorial and async-clock to LCC output delay. 11. ICC for a typical application: This parameter is tested with the device programmed as a 10-bit D-type counter. 12. Test loads are specified in Section 5 of this Data Book. 13. "Async. clock" refers to the clock from the Sum term (OR gate). 14. The "LCC" term indicates that the timing parameter is applied to the LCC register. The "IOC" term indicates that the timing parameter is applied to the IOC register. The "LCC/IOC/INC" term indicates that the timing parameter is applied to both the LCC, IOC and INC registers. 15. The term "Input" without any reference to another term refers to an (external) input pin. 16. The parameter tSPI indicates that the PCLK signal to the IOC register is always slower than the data from the pin or input by the absolute value of (tSK -tPK -tIA). This means that no set-up time for the data from the pin or input is required, i.e. the external data and clock can be sent to the device simultaneously. Additionally, the data from the pin must remain stable for tHPI time, i.e. to wait for the PCLK signal to arrive at the IOC register. 17. Typical (typ) ICC is measured at TA =25C, Freq = 25MHz, VCC =5V.
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PA7024
Ordering Information Part Number
PA7024P-15 PA7024J-15 PA7024JN-15 PA7024S-15 PA7024P-20 PA7024J-20 PA7024JN-20 PA7024S-20 PA7024PI-25 PA7024JI-25 PA7024JNI-25 PA7024SI-25 17/25ns 17/25ns 17/25ns 17/25ns I I I I 13/20ns C 10/15ns C
Speed
Temperature
Package
P24 J28 JN28 S24 P24 J28 JN28 S24 P24 J28 JN28 S24
Part Number
Device
Suffix
PA7024J-20
Package
P = Plastic 300mil DIP J = Plastic (J) Leaded Chip Carrier JN = PLCC Alternate Pin Out S = SOIC 300mil Gullwing
Speed
-15 = 10ns/15ns tpdi/tpdx -20 = 13ns/20ns tpdi/tpdx -25 = 17ns/25ns tpdi/tpdx
Temperature Range (Blank) = Commercial 0 to 70C I = Industrial -40 to +85C
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